United States Patent 5483646
 

Memory access control method and system for realizing the same

US Patent Issued on January 9, 1996
 

Inventor(s)


Assignee


Application

No. 247399 filed on 1994-05-23

Current US Class

711/100 STORAGE ACCESSING AND CONTROL

Examiners


Attorney, Agent or Firm


US Patent References

    4698750
    Security for integrated circuit microcomputer with EEPROM
    Issued on: October 6, 1987
    Inventor: Wilkie, et al.     4807119
    Memory address mapping mechanism
    Issued on: February 21, 1989
    Inventor: Suga     4891752
    Multimode expanded memory space addressing system using independently generated DMA channel selection and DMA page address signals
    Issued on: January 2, 1990
    Inventor: Fairman, et al.     5027273
    Method and operating system for executing programs in a multi-mode
    Issued on: June 25, 1991
    Inventor: Letwin     5101339
    Computer address modification system using writable mapping and page stores
    Issued on: March 31, 1992
    Inventor: Fairman, et al.

Foreign Patent References

133568 EP  Feb., 1985
2539239 FR  Jul., 1984
2595485 FR  Sep., 1987
2070821 GB  Sep., 1981

 
Abstract Claims Description Full Text

Claims

What is claimed is:

1. A memory access control system in a computer system having a memory, comprising:

central processing means for outputting a data write request, and a request for disabling memory access to a limited range of memory space addresses;

a keyboard controller, connected to said central processing means, for selectively outputting a first disable signal which disables access to the limited range of memory space addresses in response to the data write request and the request for disabling memory access;

monitoring means, connected to said central processing means, for detecting the data write request and the request for disabling memory access;

disabling means, connected to said monitoring means, for selectively generating a second disable signal which disables access to the limited range of memory space addresses in response to a detection of the data write request and the request for disabling memory access by said monitoring means; and

selecting means, connected to said keyboard controller and said disabling means, for selecting the generation of one of: the first disable signal, and the second disable signal.

2. The memory access control system according to claim 1, wherein said central processing means transmits the request for disabling memory access, to the keyboard controller without waiting for a response to the data write request from said keyboard controller.

3. The memory access control system according to claim 1, wherein the computer system includes means for initializing the system and establishing set-up data, and wherein said selecting means selects one of the first disable signal from said keyboard controller and the second disable signal from said disabling signal generating means, in accordance with selection data established in the set-up data during the system initialization.

4. A memory access control system in a computer system, wherein the computer system includes means for operating in a first address mode where memory access is enabled for address values less than a predetermined limit value, and means for operating in a second address mode where memory access is enabled for address values exceeding the predetermined limit value, said memory access control system comprising:

central processing means for transmitting a request to switch between the first and second address modes;

a keyboard controller including first switching means for switching between the first and second address modes in response to the request to switch from said central processing means;

detecting means, connected between said central processing means and said keyboard controller, for detecting the request to switch between said first and second address modes; and

second switching means for switching between said first and second address modes in response to a detection by the detecting means of the request to switch between said first and second address modes.

5. The memory access control system according to claim 4, wherein said first address mode is a real address mode, and said second address mode is a protected virtual address mode.

6. The memory access control system according to claim 4, including means for selectivity activating said first switching means and said second switching means.

7. A memory access control system for a computer system having a memory, including means for initializing the control system and establishing set-up data, the memory access control system comprising:

central processing means, having a real address mode and a protected virtual address mode, for outputting a data write request, a memory address having at least 20 digits, and a request for disabling memory access to a limited range of memory addresses in the real address mode;

keyboard controller means, connected to said central processing means, for selectively outputting a first disable signal which disables memory access to the limited range of memory address in response to the data write request and the request for disabling memory access;

monitoring means, connected to said central processing means, for detecting the data write request and request for disabling memory access;

disabling means, connected to said monitoring means, for selectively generating a second disable signal which disables memory access to the limited range of memory addresses in response to a detection of the data write request and the request for disabling memory access by said monitoring means;

selecting means, connected to said keyboard controller and said disabling means, for selecting one of: the output of the first disable signal and the output of the second disable signal in response to the set-up data; and

an AND gate for ANDing the selection of the selecting means with the 20th digit of the memory address output by the central processing means to generate a memory access output signal.

8. A memory access control system comprising:

central processing means, having a real address mode and a protected virtual address mode, for outputting a data write request, a memory address having at least 20 digits, and a request for disabling memory access to a limited range of memory addresses in the real address mode;

monitoring means, connected to said central processing means, for detecting the data write request and request for disabling memory access;

disabling means, connected to said monitoring means, for generating a disable signal which disables memory access to the limited range of memory addresses in response to a detection by said monitoring means of the data write request and the request for disabling memory access, and;

gate means for supplying a memory access disabling signal to a memory in response to the disable signal and the 20th digit of the address output from the central processing unit.

9. A memory access control system in a computer system having a memory and operated in a real address mode and a protected virtual address mode, comprising:

a keyboard controller having a function of outputting a switch signal for selectively switching the real address mode and the protected virtual address mode;

a central processing unit (CPU) for outputting to the keyboard controller a data write request, and a request for switching from the protected virtual address mode to the real address mode;

latch means for latching data for selecting one of the switching by the keyboard controller and a switching by a dedicated controller;

a dedicated controller for selectively switching the real address mode and the protected virtual address mode at a speed faster than that of the keyboard controller, the controller including:

means for detecting the data write request and the request for switching from the protected virtual address mode to the real address mode;

means for gating the data write request and the request for switching from the protected virtual address mode to the real address mode to be supplied to the keyboard controller in response to the detection by the detecting means and the data for selecting the switching by the dedicated controller latched by the latch means; and

means for generating a switching signal for switching from the protected virtual address mode to the real address mode and

means for selectively outputting the switch signal from the keyboard controller and the switch signal from the dedicated controller in response to the predetermined address.

10. A memory access control system in a computer system having a memory and operated in a real address mode and a protected virtual address mode, comprising:

a keyboard controller having a function of outputting a switch signal for selectively switching the real address mode and the protected virtual address mode;

a central processing unit (CPU) for outputting to the keyboard controller a data write request, and a request for switching from the protected virtual address mode to the real address mode;

latch means for latching data for selecting one of the switching by the keyboard controller and a switching by a dedicated controller;

a dedicated controller for selectively switching the real address mode and the protected virtual address mode at a speed faster than that of the keyboard controller, the controller including:

means for detecting the data write request and the request for switching from the protected virtual address mode to the real address mode;

means for selectively outputting the switch signal from the keyboard controller and the switch signal from the dedicated controller in response to a predetermined address; and

means for feeding back the switch signal from the dedicated controller to the keyboard controller when the latch means latches the data selecting the switching by the dedicated controller.